Explore challenges and solutions in AI chip development
Application-Specific Processors (ASIPs) for Wireless Communication SoCs
The transition from 4G to 5G brought a rethinking of architectural concepts in wireless SoCs.
The traditional split between general-purpose processors for higher layers and hardwired datapaths for lower layers is no longer efficient.
Discover how ASIPs are revolutionizing 5G SoC design by meeting high data rates, low latency requirements, and low power consumption, all while maintaining software programmability.
In this issue, learn about how ASIP Designer? helps to develop the ideal solution for computationally demanding applications with functional flexibility, joining the efficiency and performance of fixed-function hardware while maintaining software programmability, demonstrated with an LDPC decoder case study.
Also find out about the latest enhancements in the ASIP Designer W-2024.12 release, including a new simulator mode for faster cycle-accurate simulation of aggressively scheduled code, improved compiler support for RISC-V ISAs, and updates to the processor models library.
For applications requiring highly specialized processing, application-specific instruction-set processors (ASIPs) deliver greater computational efficiencies than general purpose processors and more flexibility than fixed-function RTL designs. ASIP Designer? is the leading tool solution for creating ASIPs, which might be custom processors or programmable hardware accelerators that serve in next-generation SoCs, particularly where re-programmability provides a key competitive advantage. ASIP Designer enables designers to:
Synopsys ASIP Designer: The efficient way to design, implement, program and verify your custom processor.
Learn about the ASIP Designer methodology for various application domains, including tool demos.
Take a deep dive into the processor modeling concepts and tool flows of ASIP Designer.
Access recordings of past ASIP Designer seminars and webinars on demand.
ASIP Designer comes with an extensive library of example models that can be used as a starting point for architectural exploration and customer-specific production ASIP designs, or just can be leveraged as reference implementation for selected architectural processor features.
All these example models come in source code with a fully operational toolset, SDK, baseline verification environment and are ready for push-the-button synthesizable RTL generation.