Mastering AI Chip Complexity
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Measure Delay Between Edges of a Signal
Synopsys SLM Clock & Delay Monitor (CDM) IP can be implemented in silicon with minimal area overhead. It doesn’t need any accurate high speed reference clock and provides accurate time delay measurement. It can be used for measuring clock duty cycle, memory access time, delay line characteristics, etc. It has IEEE 1500/1687 interface for connecting to test fabric. The SLM CDM IP is also available as an ISO 26262 ASIL-B ready product.
Figure 1: Synopsys SLM Clock & Delay Monitor IP
Key Features
- No high-speed high accuracy reference clock required
- Small footprint
- Available as soft IP with flexibility to customize
- EDA software automation
Key Benefits
- Clock duty cycle quality check
- Memory access time tracking with BIST
- Digital delay line test characterization
- Optimize silicon performance for safety critical applications