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From left to right: Lluis Paris of TSMC, Norman Chang of Ansys, Lalitha Immaneni of Intel, and Shekhar Kapoor of Synopsys at Chiplet Summit 2025. 

Scaling and optimization concerns

Scaling and optimization across various dimensions ¡ª down, up, and out ¡ª become critical concerns as multi-die designs grow more complex. Engineers must focus on miniaturizing components (scaling down), enhancing performance and capacity (scaling up), and expanding connectivity and integration across multiple devices or systems (scaling out).

Each of these scaling dimensions introduces unique challenges in managing power consumption, heat dissipation, signal integrity, and overall system reliability.

Immaneni said Intel is working to advance System Technology Co-Optimization (STCO) ¡ª an approach that simultaneously optimizes the interactions between system architecture, technology nodes, and design methodologies to enhance overall performance, power efficiency, and cost effectiveness in semiconductor manufacturing.

¡°If you don¡¯t pay attention to the co-optimization,¡± she said, ¡°the penalty you pay if there are issues during execution ¡ª you cannot back up from it.¡±

¡°It¡¯s a multi-scale problem,¡± added Shekhar Kapoor, executive director of product line management at Synopsys. ¡°You are scaling down, up, and out at the same time. Now you must optimize on all these different scales. And all of them have different KPIs in terms of performance, timing, electrical, thermal ¡ª even cost comes into play.¡±

Leveraging AI in multi-die design

The panelists said advances in electronic design automation (EDA) tools and methodologies are helping address multi-die challenges. AI-driven tools, in particular, are being used to optimize performance, power, and cost.

¡°You can solve problems like placement, place-and-route, architecture build-up. And you can examine the very large, multi-objective solution space and see how it speeds up the results,¡± Kapoor said of AI-assisted design optimization. ¡°We¡¯re already applying it to our 3DIC Compiler platform, where you have the opportunity to look at these die-to-die connections and communications and optimize them for signal integrity.¡±

¡°AI is helping us accelerate the research on which materials could be combined to provide beneficial behavior,¡± said Lluis Paris, senior director of IP and 3DFabric at TSMC. ¡°We¡¯re also using AI to take a large number of complex DRCs [design rule checks] and determine if they are complete.¡±

Advancing multi-die packages and industry standards

Multi-die packaging was also cited as a critical challenge, and the panelists said several obstacles must be addressed.

¡°We need to work together to solve hybrid bonding and the methodology for 3D,¡± said Paris. ¡°It is coming.¡±

¡°As you¡¯re looking at some of these complex 3DIC disaggregated technologies, I think a lot of innovations need to happen in materials,¡± Immaneni added. ¡°Delamination is an issue, how you manage thermals becomes an issue. When you¡¯re looking at a lot of high-speed I/Os, that¡¯s a challenge. You need to look at a lot of material innovation to handle that.¡±

The panelists also noted the need for ¡ª and frustrations surrounding ¡ª industry standards.

¡°One of the biggest challenges we see are the UCIe variations, or the external memory,¡± Immaneni said. ¡°They need to be certified for the packaging technologies that exist.¡±

¡°In the case of UCIe, I fully agree with the value of the standard. I can also tell you that¡¯s not what we see happening in the market,¡± said Paris, noting customers favor the UCIe PHY for its efficient power performance but tend to overlook standard protocols.

Coalescing research and skillsets

According to the panelists, taming multi-die design complexity and accelerating innovation will require broad industry collaboration and an evolution of skillsets.

¡°1,000 chiplets is not too far away. Maybe just two or three years away,¡± Chang said. ¡°There is so much research that we need to perform. We need to work with universities and we need to work with Synopsys to realize this vision.¡±

Workflows and engineering skills must also coalesce.

¡°If you look at the skillsets of the engineers that are growing and innovating, it¡¯s no longer siloed,¡± said Immaneni. ¡°You don¡¯t have a silicon architect, packaging architect, platform architect. It¡¯s all meshing.¡±

¡°You need to be a generalist,¡± added Paris. ¡°The value is ¡®in between¡¯ expertise. If you are very deep and very narrow, it¡¯s not going to help because these are new problems that are not well defined.¡±

¡°Don¡¯t think like an engineer, think like an innovator,¡± Kapoor concluded. ¡°Technical skills are essential, but so is creativity. That¡¯s why we need the ecosystem. It¡¯s all about that. Without that, you can¡¯t achieve anything.¡±