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Highlights

• Native SystemVerilog/Verilog with UVM
• Includes primary, secondary, monitor
• Runs natively on all major simulators
• Built-in UVM sequence library
• Verdi? protocol aware debug

Key Features

AXI Interconnect Test Suites Available

• Trace Data Transfer (Valid, ready signaling) 
• Narrow Trace Data Transfer (Data Valid Bytes signaling) 
• Flow Control (Valid, ready signaling) 
• Flush Request Response (Flush Valid, Ready signaling with Data transfer) 
• Synchronization Request capture and pass to Trace Source (i.e. Sequence layer) 
• Secondary Random Response for Trace Data Transfer 
• Secondary Random Flush Request Generation 
• Secondary Random Synchronization Request Generation 
• Secondary Memory (for Trace Data capture)