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Mastering AI Chip Complexity
Mastering AI Chip Complexity

Explore challenges and solutions in AI chip development

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Innovate Faster with Synopsys Multi-Die Solution

Accelerating success from early architecture to manufacturing.

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SNUG Silicon Valley 2025
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From this Author

Maria Auras-Rodriguez

Maria Auras-Rodriguez

Maria joined the ASIP Designer R&D Team in 2019 where she focuses on the ASIP Designer’s HDL Generator tool, including synthesis support for ASIPs. She has a master's degree in Embedded Systems Design from ALaRI, University of Lugano. Before joining Synopsys, she worked as a researcher at the Institute for Communication Technologies and Embedded Systems (ICE) at RWTH Aachen University.