Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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2019 论文集
2019 论文集
Honorable
A method to accelerate ECO timing closure
Functional equivalence checking for different implementations of FIFOs using ESP
Variational Timing Signoff Accuracy Verification using PrimeTime and HSPICE
Synopsys LPDDR4X multiPHY Flip-Chip Design with ICC2 Multiple Levels of Physical Hierarchy Flow (MPH)
Tips to Improve Test Point Accuracy of SpyGlass DFT
Advanced Fusion Technology in IC Compiler II Delivers Higher-density Design
Implementation of High-congestion Design by ICC2
一种基于 PT HyperScale 适用于大规模设计的混合静态时序分析方法
Regression Testing For ICC2 Power Optimization
High Performance Design Evaluation Using Hspice PT and ICC2 at Advanced Nodes
POCV-LVF Std-Cell Characterization,Qualification and Correlation Automotive flow with SiliconSmart and PrimeTime
SoC Verification Quantitative Closed-loop Management Based on Automation and DPI-C Library
High Performance UNIT FPGA Prototyping on HAPS Platform
Speed up various soc checks using Vlink flow based on Verdi vc-Apps
Accelerate HDMI 2.1 verification using Synopsys Source and Sink HDMI VIP
Virtual Prototyping for AI Chip Early SW Development and Testing
Using VC-SEQ to Verify Netlist Patches for Low Power
The implementation of SMx algorithms using APEX on ARC processors
Implementation and performance improvement of Latch Based CPU Design with IC Complier II
Presentations
Full Flow Physical Verification Productivity Using IC Validator
ECO Fusion Drive Faster Signoff Closure and Eliminate ECO Iterations
RTL Synthesis for the Next Decade
Designing SoCs for Autonomous-Drive and ADAS
Avoid Silicon Failure with Netlist CDC Verification
Make Sure Your Design is Robust Enough Against Variations
AI-Enabled PrimeTime for AI Designs
Consulting Services Enabling Automotive SoC Certification for Functional Safety