Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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2021 论文集
2021 论文集
Bronze
Accelerate Pre-Silicon Power Analysis with ZeBu Empower
Critical ICG Timing Optimization in ICC2
FMECO Technology Application in the Complex Function ECO of Chip Design
Using Hybrid Flow for CDC Functional Verification Closure
Using Formal Datapath Verification to Verify GPU Instruction’s Exceptions Under IEEE 754 Standard
Honorable
Accelerating AI SoC System Level Validation and Early Software Development using HAPS Prototyping Solution
Accelerating Automotive SoC FuSa Verification with Synopsys Solution
An Implementation of using Synopsys MIPI DPHY with user-defined MIPI CSI2/DSI Combo TX Controller
Best Practices Using Fusion Compiler to Achieve Best PPA for Arm Core Processer Implementation
Camera Subsystem Set-Up On HAPS-100
Customized Design Flows on Custom Compiler for Advanced Nodes
GlobalFoundries?12LP&12LP+ Cortex-A75 Single-core CPU PPA Benchmark
GlobalFoundries?22FDX Application-Optimized Solution
Haps Design Porting Validation using VC Formal SEQ
Use Unified Topology Language to Accelerate Large Scale Network Chip Complexity Feedthrough Implementation
Using ChipInt from Verdi to do Integration in SoC
Using STAR MMB Processor to Test Memory on Custom Shared-Test-Bus
Using VC ExecMan and Verdi Planner for Intelligent Verification Closed-Loop Management
Using VC Formal AIP to Promote Efficiency of IP Verification
Using VCS-ICO to Boost Verification Functional Coverage Convergence Efficiency
Utilizing TestMAX SMS Test Algorithm Programmability to Reduce Unnecessary Timing Signoff Effort on Two-Port Memories
VCS-TLI and CoFluent: Unleash Power of SystemC/UVM Co-simulation
Presentations
Automotive Functional Safety
Build Security in Automotive Development Lifecycle
Catch Bugs Early with Synopsys Verification Continuum
Challenges in 2.5D/3D Design
Enabling Innovative Power-Aware Test and Diagnosis Capabilities for Digital Logic and Memory with the Synopsys TestMAX Solution
Enabling Next-Level Insight in SoC Designs and Systems with Silicon Lifecycle Management, Analytics and Embedded Sensing
Fast and Predictable RTL PPA Tuning using RTL Architect
Faster Analog Design Closure with Early Parasitic Analysis Flow in Synopsys Custom Design Platform
HAPS100 + HAPS80 Mixed System
Is Formal Signoff a Reality?
PPA(V) Tutorial: PPA Optimization as a Function of Operating Voltage
PrimeTime Signoff Leadership
PrimeSim Continuum
Shift-Left LVS Closure
Speedup HW/SW Verification For Automotive SoC Designs
Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis
Synopsys End-to-End Low Power Solution
Transformative Fusion Digital Implementation Technologies Fueling The Next Phase of Silicon Design Innovation
VC SpyGlass–Next Generation Static Platform
Verifying Multi-processor SoC Cache Coherency using Synopsys AMBA5 Verification Solution
构建高效高质AI 芯片软件
功能安全标准在半导体行业中的应用